In designing ESD clamps two important parameters to consider are the triggering voltage at which the ESD clamp triggers, and the holding voltage, which defines the voltage below which the clamp no longer conducts after an ESD event and thus avoids latch up. The present invention seeks to provide a clamp based on NMOS devices which inherently have high holding voltage characteristics and which thus make the clamp resistant to latch-up.
Furthermore, many applications, such as amplifiers, interface products, display column drivers, level shifters, and automotive applications require ESD protection in both directions to protect against both positive and negative ESD pulses. The present invention seeks to provide a dual direction ESD clamp.
Also, many of the ESD protection solutions that have been developed in the past have relied on SCR devices. However, these require the implementation of a non-self-aligned device architecture, which complicates the implementation of a system level protection.